| 24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390, 2019 | 264 | 2019 |
| 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019 | 226 | 2019 |
| 15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices CX Xue, TY Huang, JS Liu, TW Chang, HY Kao, JH Wang, TW Liu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 244-246, 2020 | 211 | 2020 |
| CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors WH Chen, C Dou, KX Li, WY Lin, PY Li, JH Huang, JH Wang, WC Wei, ... Nature Electronics 2 (9), 420-428, 2019 | 194 | 2019 |
| 15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... 2020 IEEE international solid-state circuits conference-(ISSCC), 246-248, 2020 | 181 | 2020 |
| A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... IEEE Journal of Solid-State Circuits 55 (1), 189-202, 2019 | 156 | 2019 |
| A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices CX Xue, YC Chiu, TW Liu, TY Huang, JS Liu, TW Chang, HY Kao, ... Nature Electronics 4 (1), 81-90, 2021 | 101 | 2021 |
| Embedded 1-Mb ReRAM-based computing-in-memory macro with multibit input and weight for CNN-based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... IEEE Journal of Solid-State Circuits 55 (1), 203-215, 2019 | 80 | 2019 |
| A 4-Kb 1-to-8-bit configurable 6T SRAM-based computation-in-memory unit-macro for CNN-based AI edge processors YC Chiu, Z Zhang, JJ Chen, X Si, R Liu, YN Tu, JW Su, WH Huang, ... IEEE Journal of Solid-State Circuits 55 (10), 2790-2801, 2020 | 74 | 2020 |
| Ai edge devices using computing-in-memory and processing-in-sensor: from system to device TH Hsu, YC Chiu, WC Wei, YC Lo, CC Lo, RS Liu, KT Tang, MF Chang, ... 2019 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2019 | 37 | 2019 |
| Considerations of integrating computing-in-memory and processing-in-sensor into convolutional neural network accelerators for low-power edge devices KT Tang, WC Wei, ZW Yeh, TH Hsu, YC Chiu, CX Xue, YC Kuo, TH Wen, ... 2019 Symposium on VLSI Circuits, T166-T167, 2019 | 33 | 2019 |
| A 55nm 1-to-8 bit configurable 6T SRAM based computing-in-memory unit-macro for CNN-based AI edge processors Z Zhang, JJ Chen, X Si, YN Tu, JW Su, WH Huang, JH Wang, WC Wei, ... 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 217-218, 2019 | 21 | 2019 |
| A 0.5 V real-time computational CMOS image sensor with programmable kernel for always-on feature extraction TH Hsu, YK Chen, TH Wen, WC Wei, YR Chen, FC Chang, H Kim, ... 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 33-34, 2019 | 17 | 2019 |
| A relaxed quantization training method for hardware limitations of resistive random access memory (ReRAM)-based computing-in-memory WC Wei, CJ Jhang, YR Chen, CX Xue, SH Sie, JL Lee, HW Kuo, CC Lu, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6 …, 2020 | 12 | 2020 |
| A neuromorphic computing system for bitwise neural networks based on ReRAM synaptic array PY Li, CH Yang, WH Chen, JH Huang, WC Wei, JS Liu, WY Lin, TH Hsu, ... 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2018 | 3 | 2018 |
