Garvit Juniwal
Garvit Juniwal
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Zitiert von
Zitiert von
Syntax-guided synthesis
R Alur, R Bodik, G Juniwal, MMK Martin, M Raghothaman, SA Seshia, ...
2013 Formal Methods in Computer-Aided Design, 1-8, 2013
Robust online monitoring of signal temporal logic
JV Deshmukh, A Donzé, S Ghosh, X Jin, G Juniwal, SA Seshia
Formal Methods in System Design 51, 5-30, 2017
ddnf: An efficient data structure for header spaces
N Bjørner, G Juniwal, R Mahajan, SA Seshia, G Varghese
Hardware and Software: Verification and Testing: 12th International Haifa …, 2016
CPSGrader: Synthesizing temporal logic testers for auto-grading an embedded systems laboratory
G Juniwal, A Donzé, JC Jensen, SA Seshia
Proceedings of the 14th International Conference on Embedded Software, 1-10, 2014
Syntax-guided synthesis. To Appear in Marktoberdrof NATO proceedings, 2014
R Alur, R Bodik, E Dallal, D Fisman, P Garg, G Juniwal, H Kress-Gazit, ...
Finding instability in biological models
B Cook, J Fisher, BA Hall, S Ishtiaq, G Juniwal, N Piterman
Computer Aided Verification: 26th International Conference, CAV 2014, Held …, 2014
Quantitative network analysis
G Juniwal, N Bjorner, R Mahajan, S Seshia, G Varghese
Technical report, 2016
Clustering-Based Active Learning for CPSGrader
G Juniwal, S Jain, A Donzé, SA Seshia
Proceedings of the Second (2015) ACM Conference on Learning@ Scale, 399-403, 2015
CPSGrader: Auto-grading and feedback generation for cyber-physical systems education
G Juniwal
Master’s thesis, EECS Department, University of California, Berkeley, 2014
Reactive synthesis using sketching
G Juniwal
Technical report, UC Berkeley, 2012
Probablistic methods as a proof technique
G Juniwal, P Kamath, N Totla
Automated refinement of executable biological models
BA Hall, G Juniwal, ACE Dahl, J Fisher
review, 2005
Robust Online Monitoring of Signal Temporal Logic
G Juniwal, S Ghosh, A Donzé, SA Seshia, JV Deshmukh, X Jin
CPSGrader: Synthesizing Temporal Logic Testers for Auto-Grading
A Donzé, G Juniwal, JC Jensen, SA Seshia
Clustering-Based Active Learning
G Juniwal, S Jain
Decidability of Emptiness Checking in various Alternating Timed Automata and Connections to Timed Logics
G Juniwal
Indian Institute of Technology, Bombay Mumbai, 0
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