Miguel Arias-Estrada
Miguel Arias-Estrada
Computer Science
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Zitiert von
Zitiert von
Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling
MA Nuño-Maganda, MO Arias-Estrada
2005 International Conference on Reconfigurable Computing and FPGAs …, 2005
Fast three dimensional recovery method and apparatus
M Arias-Estrada, A Morales-Reyes, ML Rosas-Cholula, G Sosa-Ramirez
US Patent 7,769,205, 2010
Real-time image processing with a compact FPGA-based systolic architecture
C Torres-Huitzil, M Arias-Estrada
Real-time imaging 10 (3), 177-187, 2004
Integrated motion vision sensor
M Arias-Estrada
US Patent 6,253,161, 2001
FPGA-based configurable systolic architecture for window-based image processing
C Torres-Huitzil, M Arias-Estrada
EURASIP Journal on Advances in Signal Processing 2005, 1-11, 2005
An FPGA architecture for high speed edge and corner detection
C Torres-Huitzil, M Arias-Estrada
Proceedings Fifth IEEE International Workshop on Computer Architectures for …, 2000
FPGA-based detection of SIFT interest keypoints
L Chang, J Hernández-Palancar, LE Sucar, M Arias-Estrada
Machine vision and applications 24, 371-392, 2013
Real-time field programmable gate array architecture for computer vision
M Arias-Estrada, C Torres-Huitzil
Journal of Electronic Imaging 10 (1), 289-296, 2001
An FPGA co-processor for real-time visual tracking
M Arias-Estrada, E Rodríguez-Palacios
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002
Compact spiking neural network implementation in FPGA
S Maya, R Reynoso, C Torres, M Arias-Estrada
Field-Programmable Logic and Applications: The Roadmap to Reconfigurable …, 2000
An FPGA stereo matching unit based on fuzzy logic
M Pérez-Patricio, A Aguilar-González, M Arias-Estrada, ...
Microprocessors and Microsystems 42, 87-99, 2016
Iterative closest SIFT formulation for robust feature matching
R Lemuz-López, M Arias-Estrada
International Symposium on Visual Computing, 502-513, 2006
Multiple stereo matching using an extended architecture
M Arias-Estrada, JM Xicotencatl
International Conference on Field Programmable Logic and Applications, 203-212, 2001
FPGA processor for real-time optical flow computation
S Maya-Rueda, M Arias-Estrada
Field Programmable Logic and Application: 13th International Conference, FPL …, 2003
Input and/or output pruning of composite length FFTs using a DIF-DIT transform decomposition
M Medina-Melendrez, M Arias-Estrada, A Castro
IEEE Transactions on Signal Processing 57 (10), 4124-4128, 2009
FPGA-based customizable systolic architecture for image processing applications
G Saldana, M Arias-Estrada
2005 International Conference on Reconfigurable Computing and FPGAs …, 2005
Mayfly Optimization Algorithm Applied to the Design of PSS and SSSC‐POD Controllers for Damping Low‐Frequency Oscillations in Power Systems
EV Fortes, LFB Martins, MVS Costa, L Carvalho, LH Macedo, R Romero
International Transactions on Electrical Energy Systems 2022 (1), 5612334, 2022
An FPGA 2D-convolution unit based on the CAPH language
A Aguilar-González, M Arias-Estrada, M Pérez-Patricio, ...
Journal of Real-Time Image Processing 16, 305-319, 2019
Motion vision sensor architecture with asynchronous self-signaling pixels
M Arias-Estrada, D Poussart, M Tremblay
Proceedings Fourth IEEE International Workshop on Computer Architecture for …, 1997
FPGA based acceleration for image processing applications
G Saldaña-González, M Arias-Estrada
Image Processing, 477-492, 2009
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