| High Level Synthesis of Complex Applications: An H. 264 Video Decoder X Liu, Y Chen, T Nguyen, S Gurumani, K Rupnow, D Chen Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 66 | 2016 |
| Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs D Chen, J Cong, S Gurumani, W Hwu, K Rupnow, Z Zhang IET Cyber-Physical Systems: Theory & Applications 1 (1), 70-77, 2016 | 65 | 2016 |
| Fast and effective placement and routing directed high-level synthesis for FPGAs H Zheng, ST Gurumani, K Rupnow, D Chen Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 54 | 2014 |
| High-Level Synthesis With Behavioral-Level Multicycle Path Analysis H Zheng, ST Gurumani, L Yang, D Chen, K Rupnow IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 39 | 2014 |
| High-level Synthesis with Behavioral level Multi-Cycle Path Analysis H Zheng, ST Gurumani, L Yang, D Chen, K Rupnow IEEE International Conference on Field Programmable Logic and Applications, FPL, 2013 | 39 | 2013 |
| Hardware coprocessor synthesis from an ansi c specification S Ahuja, ST Gurumani, C Spackman, SK Shukla IEEE Design & Test of Computers 26 (4), 58-67, 2009 | 29 | 2009 |
| FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Y Chen, ST Gurumani, Y Liang, G Li, D Guo, K Rupnow, D Chen IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2015 | 27 | 2015 |
| High Level Synthesis of Multiple Dependent CUDA Kernels for FPGAs ST Gurumani, K Rupnow, Y Liang, H Cholakkai, D Chen IEEE/ACM Asia and South Pacific Design Automation Conference, 2013 | 26 | 2013 |
| JIT Trace-Based Verification for High-Level Synthesis L Yang, M Ikram, S Gurumani, S Fahmy, D Chen, K Rupnow International Conference on Field-Programmable Technology, 2015 | 21 | 2015 |
| Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++ ST Gurumani, A Milenkovic Proceedings of the 42nd annual Southeast regional conference, 261-266, 2004 | 21 | 2004 |
| AutoSLIDE: Automatic source-level instrumentation and debugging for HLS L Yang, S Gurumani, D Chen, K Rupnow 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom …, 2016 | 17 | 2016 |
| AutoSLIDE: Automatic source-level instrumentation and debugging for HLS L Yang, S Gurumani, D Chen, K Rupnow 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom …, 2016 | 17 | 2016 |
| Real-time system-level implementation of a telepresence robot using an embedded GPU platform MT Satria, S Gurumani, W Zheng, KP Tee, A Koh, P Yu, K Rupnow, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 14 | 2016 |
| Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation K Campbell, L He, L Yang, S Gurumani, K Rupnow, D Chen Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 13 | 2016 |
| FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler T Nguyen, S Gurumani, K Rupnow, D Chen Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 11 | 2016 |
| System-Level Design Solutions: Enabling the IoT Explosion L Yang, Y Chen, W Zuo, T Nguyen, S Gurumani, K Rupnow, D Chen International Conference on ASIC, 2015 | 11 | 2015 |
| Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis Z Sun, K Campbell, W Zuo, K Rupnow, S Gurumani, F Doucet, D Chen 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 218-225, 2016 | 9 | 2016 |
| Behavioral-Level IP Integration in High-Level Synthesis L Yang, S Gurumani, D Chen, K Rupnow International Conference on Field-Programmable Technology, 2015 | 8 | 2015 |
| Integrated CUDA-to-FPGA Synthesis with Network-on-Chip ST Gurumani, J Tolar, Y Chen, E Liang, K Rupnow, D Chen 22nd IEEE International Symposium on Field-Programmable Custom Computing …, 2014 | 7 | 2014 |
| FCUDA-Bus: Hierarchical and Scalable Bus Architecture Generation on FPGAs with High-Level Synthesis Y Chen, T Nguyen, Y Chen, S Gurumani, Y Liang, K Rupnow, J Cong, ... IEEE, 2016 | 6* | 2016 |
Kyle RupnowASIC Architect, GoogleBestätigte E-Mail-Adresse bei google.com
