| An FPGA-based parallel sorting architecture for the Burrows Wheeler transform J Martinez, R Cumplido, C Feregrino 2005 International Conference on Reconfigurable Computing and FPGAs …, 2005 | 79 | 2005 |
| FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256 I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval Microprocessors and Microsystems 37 (6-7), 750-757, 2013 | 65 | 2013 |
| Pipelined CORDIC design on FPGA for a digital sine and cosine waves generator EO Garcia, R Cumplido, M Arias 2006 3rd international Conference on Electrical and Electronics Engineering, 1-4, 2006 | 62 | 2006 |
| On the design of an FPGA-Based OFDM modulator for IEEE 802.11 a J Garcia, R Cumplido 2005 2nd International Conference on Electrical and Electronics Engineering …, 2005 | 59 | 2005 |
| A compact FPGA-based processor for the Secure Hash Algorithm SHA-256 R García, I Algredo-Badillo, M Morales-Sandoval, C Feregrino-Uribe, ... Computers & Electrical Engineering 40 (1), 194-202, 2014 | 57 | 2014 |
| A versatile linear insertion sorter based on an FIFO scheme R Perez-Andrade, R Cumplido, C Feregrino-Uribe, FM Del Campo Microelectronics Journal 40 (12), 1705-1713, 2009 | 54 | 2009 |
| On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004 J Garcia, R Cumplido 2005 International Conference on Reconfigurable Computing and FPGAs …, 2005 | 43 | 2005 |
| Decision tree based FPGA-architecture for texture sea state classification S Lopez-Estrada, R Cumplido 2006 IEEE International Conference on Reconfigurable Computing and FPGA's …, 2006 | 42 | 2006 |
| FPGA hardware architecture of the steganographic context technique E Gómez-Hernández, C Feregrino-Uribe, R Cumplido 18th International Conference on Electronics, Communications and Computers …, 2008 | 41 | 2008 |
| On the implementation of an efficient FPGA-based CFAR processor for target detection R Cumplido, C Torres, S Lopez (ICEEE). 1st International Conference on Electrical and Electronics …, 2004 | 38 | 2004 |
| An area/performance trade-off analysis of a GF (2m) multiplier architecture for elliptic curve cryptography M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo Computers & Electrical Engineering 35 (1), 54-58, 2009 | 34 | 2009 |
| Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11 i standard I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval Computers & Electrical Engineering 36 (3), 565-577, 2010 | 29 | 2010 |
| Area/performance trade-off analysis of an FPGA digit-serial GF (2m) Montgomery multiplier based on LFSR M Morales-Sandoval, C Feregrino-Uribe, P Kitsos, R Cumplido Computers & Electrical Engineering 39 (2), 542-549, 2013 | 28 | 2013 |
| FPGA implementation and performance evaluation of AES-CCM cores for wireless networks I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval 2008 International Conference on Reconfigurable Computing and FPGAs, 421-426, 2008 | 27 | 2008 |
| A reconfigurable GF(2M) elliptic curve cryptographic coprocessor M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo 2011 VII Southern Conference on Programmable Logic (SPL), 209-214, 2011 | 26 | 2011 |
| High payload data-hiding in audio signals based on a modified OFDM approach JJ Garcia-Hernandez, R Parra-Michel, C Feregrino-Uribe, R Cumplido Expert Systems with Applications 40 (8), 3055-3064, 2013 | 25 | 2013 |
| Compact FPGA hardware architecture for public key encryption in embedded devices L Rodríguez-Flores, M Morales-Sandoval, R Cumplido, C Feregrino-Uribe, ... PloS one 13 (1), e0190939, 2018 | 23 | 2018 |
| A configurable FPGA-based hardware architecture for adaptive processing of noisy signals for target detection based on constant false alarm rate (CFAR) algorithms R Cumplido, C Torres, S López Global signal processing conference, 214-218, 2004 | 22 | 2004 |
| FPGA/GPU-based acceleration for frequent itemsets mining: A comprehensive review L Bustio-Martínez, R Cumplido, M Letras, R Hernández-León, ... ACM Computing Surveys (CSUR) 54 (9), 1-35, 2021 | 21 | 2021 |
| A Compact FPGA‐Based Accelerator for Curve‐Based Cryptography in Wireless Sensor Networks M Morales-Sandoval, LAR Flores, R Cumplido, JJ Garcia-Hernandez, ... Journal of Sensors 2021 (1), 8860413, 2021 | 21 | 2021 |
