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Horacio Neto
Horacio Neto
INESC-ID / IST, University of Lisbon
Bestätigte E-Mail-Adresse bei inesc-id.pt - Startseite
Titel
Zitiert von
Zitiert von
Jahr
Macro-based hardware compilation of Java< sup> TM</sup> bytecodes into a dynamic reconfigurable computing system
JMP Cardoso, HC Neto
Field-Programmable Custom Computing Machines, 1999. FCCM'99. Proceedings …, 1999
1321999
Trends of CPU, GPU and FPGA for high-performance computing
M Vestias, H Neto
2014 24th International Conference on Field Programmable Logic and …, 2014
1302014
Compilation for FPGA-based reconfigurable hardware
JMP Cardoso, HC Neto
IEEE Design & Test of Computers 20 (2), 65-75, 2003
822003
An exact solution to the minimum size test pattern problem
PF Flores, H Neto, JP Marques Silva
International Conference on Computer Design: VLSI in Computers and …, 1998
781998
Moving deep learning to the edge
MP Véstias, RP Duarte, JT de Sousa, HC Neto
Algorithms 13 (5), 125, 2020
622020
Sorting units for FPGA-based embedded systems
R Marcelino, H Neto, JMP Cardoso
IFIP Working Conference on Distributed and Parallel Embedded Systems, 11-22, 2008
552008
An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs
JMP Cardoso, HC Neto
VLSI: Systems on a Chip: IFIP TC10 WG10. 5 Tenth International Conference on …, 2000
502000
A full featured configurable accelerator for object detection with YOLO
D Pestana, PR Miranda, JD Lopes, RP Duarte, MP Véstias, HC Neto, ...
IEEE Access 9, 75864-75877, 2021
462021
Decimal multiplier on FPGA using embedded binary multipliers
HC Neto, MP Véstias
2008 International Conference on Field Programmable Logic and Applications …, 2008
442008
An efficient and scalable architecture for neural networks with backpropagation learning
PO Domingos, FM Silva, HC Neto
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
432005
Parallel decimal multipliers using binary multipliers
MP Véstias, HC Neto
2010 VI Southern Programmable Logic Conference (SPL), 73-78, 2010
412010
Parallel dot-products for deep learning on FPGA
M Véstias, RP Duarte, JT de Sousa, H Neto
2017 27th international conference on field programmable logic and …, 2017
362017
Multi-core for K-means clustering on FPGA
J Canilho, M Véstias, H Neto
2016 26th International Conference on Field Programmable Logic and …, 2016
352016
On applying set covering models to test set compaction
PF Flores, HC Neto, JP Marques-Silva
Proceedings Ninth Great Lakes Symposium on VLSI, 8-11, 1999
351999
kNN-STUFF: kNN STreaming Unit for Fpgas
J Vieira, RP Duarte, HC Neto
IEEE Access 7, 170864-170877, 2019
322019
A review of synthetic-aperture radar image formation algorithms and implementations: A computational perspective
H Cruz, M Véstias, J Monteiro, H Neto, RP Duarte
Remote Sensing 14 (5), 1258, 2022
282022
Double-precision gauss-jordan algorithm with partial pivoting on fpgas
R Duarte, H Neto, M Véstias
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
282009
Towards an automatic path from Java< sup> TM</sup> bytecodes to hardware through high-level synthesis
JMP Cardoso, HC Neto
Electronics, Circuits and Systems, 1998 IEEE International Conference on 1 …, 1998
281998
Area and performance optimization of a generic network-on-chip architecture
MP Véstias, HC Neto
Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006
272006
On reconfigurable architectures for efficient matrix inversion
GM De Matos, HC Neto
2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006
252006
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